ISPEC 2024 - Pictures

ISPEC 2024 - Posters

About ISPEC 2024

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Welcome to ISPEC and Welcome to a New Semicon India
For Next Generation of Semiconductors, Packaging and Systems R&D & Educated Workforce

...

Thanks to the visionary leadership of Hon. PM Modi Ji and Hon. Ministers Ashwini Vaishnav Ji & Rajeev Chandrashekar Ji, India is poised to become a global hub for semiconductors, packaging and systems (SPS) through their ISM initiative. I’m honored to have been chosen by them as an expert technical advisor and academic R&D leader to transform Indian electronics in my field of integrated systems packaging. India has all the fundamentals to be a global leader. It is correcting its two weaknesses in R&D and manufacturing technologies and expertise, through the ISM initiative. India has a well-educated workforce in basic sciences and engineering, unparalleled expertise, and resources in design and software. Global companies are very much interested in investing in India to design, develop and manufacture high-quality and cost-effective electronic products. The ISPEC conference brings the entire ecosystem of researchers, developers, suppliers, manufacturers and users together along with government and industry executives to make this happen

Technical Vision: A technical vision for India can be semiconductors, packaging or systems, or combining all to form integrated systems, integrating devices and system components into integrated system packages to serve a variety of strategic needs in four areas:

  • • Automotive including power electronics with compound semiconductors
  • • Computing and AI
  • • 6G and beyond communications, and
  • • Integrated sensors for IoT, medical and other applications

This integrated systems vision has the best potential to transform India from its current design-centric model at device level to system-centric model, from system design, fabrication, integration, assembly, and test to form end products that serve both growing domestic and global markets. This is particularly true, as the global industry moves into post Moore’s Law devices and systems which are currently at < 2nm in R&D and which provide <15% transistor performance improvement from node to node, in contrast to a 35% improvement during the peak of Moore’s Law, thus reinforcing the integrated systems vision.

Strategy to Attract Global Industry to India: Most domestic and foreign companies in India today are only focused on design and software. This is a small fraction of India’s capabilities. With the new focus on large scale R&D and manufacturing of semiconductors, packaging and systems, India is expected to grow its electronics market by 6-10x in the next ten years. Because of this and other reasons, India expects to be the 3rd largest economy by 2030. In addition, India believes it can be one of the lowest-cost electronics producers. All these are compelling reasons for global industry to invest in R&D and educated workforce for the global industry, paving the way for the next generation of manufacturing.

...

All this can happen only if we can attract a large number of global companies to India. The best way for India to attract a large number of global companies is if India invests in the infrastructure for large scale R&D and workforce development in all the strategic system designs and technologies, needed by global companies. This is the first reason. This is beginning to happen with the proposed infrastructure from ISM. The second reason for global companies to want to come to India is if Indian academic institutions perform large scale, global level R&D, unlike almost any other country, using its crown jewels—IITs and IISc’s, and private colleges and universities. But this R&D must be at a global level and for the next generation of global industry needs. As we all know, the Indian institutions have been producing the very best engineers in the world over the last four decades including those who are now CEOs, CTOs, and technical leaders of many large global companies like IBM, Google, Microsoft, Micron, and Western Digital, to name a few. Their focus in phase one so far has been largely on workforce development. In phase two, they are completely capable of focusing on the two most important ingredients for global industry that no other organization can deliver: 1) developing the next generation of technologies the global industry needs and 2) educating students in those technologies. So the focus in phase two must be on industry-driven R&D and workforce development.

Georgia Tech PRC Industry Consortium Model to Transform Indian Semiconductors and Packaging: Traditionally, all top global universities perform high quality academic research addressing scientific and technical challenges that result in educating students, and publications in peer-reviewed journals. A small fraction of these, about 5%, result in discoveries and inventions that end up in products over the next 20 years. So there exist a gap known widely as the “valley of death” between academic R&D and industry’s need for manufacturing to make competitive products. To address this valley of death gap, many countries have created industrial institutes like Fraunhofer in Germany, ITRI in Taiwan, IME in Singapore and many others to develop industry-needed, ready-to manufacture technologies and transfer these to participating companies. They have been very successful, but their focus is technology development and scale-up, and not research to explore new concepts to make new products. They also don’t produce a workforce in any significant way. In the U.S., Semiconductor Research Corporation (SRC) is created to explore new long-term strategic frontiers to provide roadmap solutions for companies. Learning from all these and others, I have created an industry-academic-government (both state and federal) model at Georgia Tech that combines all the above and, in addition, develops programs that produce a large number of well-educated, cross-disciplinary, systems engineers at B.S., M.S. and Ph.D. levels. Georgia Tech was unique in that, it not only explored and demonstrated new individual strategic technologies, but also integrated these technologies into system prototypes and in so doing so, educated thousands of engineers at both technology and system integration levels. Georgia Tech is the first and perhaps the only university to have developed this model on such a large scale. But this model required more than faculty and students. It required full-time research faculty and on-campus industry engineers assigned by their global companies and it required state-of-the-art infrastructure, performing leading edge strategic R&D and advanced prototypes in the state-of-the-art experimental and pilot facilities.

As an advisor to ISM, I have begun to apply the Georgia Tech model in India through a 10-step process to set-up an industry consortium for large scale, global level, next generation R&D in 12 strategic SPS technologies involving 50-100 faculty from 13 top IITs and IISc’s and selective private colleges and universities, 24 academic experts from many well-known industry-centric R&D centers in the U.S., Europe and Asia, and 50 global companies. We have made outstanding progress and are ready to form an industry consortium in partnership with global SPS companies in India mid next year.

...

Benefits to Global Industry: There are many benefits to the global industry. The two most important are:

Workforce: A large number of well-educated students that are well- prepared in all strategic system design and technologies who can hit the ground running when they join companies upon graduation. A well-educated workforce is the single biggest current barrier to worldwide semiconductor, packaging and systems market growth.

Next Generation SPS Technologies: Large scale R&D, with intellectual property, developed jointly in partnership with the global industry thus addressing the strategic needs of the global industry. Supply chain companies can benefit by growing their R&D and manufacturing businesses, as India grows its electronics-based industry. India plans to invest $10B in manufacturing to start within, the next two years. Many global companies shown in Fig. 4 are interested in being part of both R&D and workforce programs.

...

Companies can benefit greatly from these large and historic investments by Government of India by simply using a small fraction of their CSR funds and by advising and guiding Indian faculty and students. The best way to begin this journey is ISPEC participation.

ISPEC Conference and Sessions: ISPEC brings and begins to create a complete ecosystem consisting of researchers, developers, manufacturers, suppliers and users in India. It is also the purpose of the conference for Indian and global collaborating faculty to propose about 50 next generation R&D projects in the 12 SRAs to about 50 participating global companies that are in attendance. The ISPEC conference begins today with the inaugural session, followed by industry and academic keynote talks and finishing with the director’s session. Day 2 is dedicated to R&D proposals to global industry by means of presentations and poster papers. Day 3 starts with a presentation on R&D and education infrastructure necessary in India, followed by workforce development programs. The last session brings global suppliers from the U.S., Europe, Japan, Korea, Taiwan and Singapore in materials, processes and tools to form R&D and manufacturing partnerships in integrated systems.

Welcome To ISPEC and Welcome To The New Semiconductor Nation!

Prof. Rao R. Tummala

  • • Advisor to ISM
  • • Champion for Large Scale, Global-level R&D and Workforce Development in India
  • • Emeritus Professor and Founding Director, Georgia Tech
  • • Former IBM Fellow and Director of Packaging, IBM

Purpose of Conference

As India enters semiconductor and package manufacturing with $10B incentives by ISM, India needs to develop the entire ecosystem, from Design to R&D to manufacturing, products, applications, and services, as well as workforce development. This ecosystem requires researchers, developers, supply-chain manufacturers for materials and tools, as well as manufacturers and users. This is the purpose of the 1st Indian Semiconductor and Packaging Eco-System Conference (ISPEC), with a focus on global level R&D and workforce development in partnership with global industry, leading to a large-scale Industry–Academic consortium in next generation of semiconductors, packaging, and systems in India.

Technical Focus

The focus of strategic R&D in India is in Integrated semiconductors and systems packaging for such emerging large-scale product sectors as computing and AI, 6G and beyond communications, ultra-high-power modules for electric cars, and integrated sensors for IoT and medical electronics. Such product sectors require next generation, global level R&D, education and skill development, and global industry partnerships spanning from system design and 3D architectures to devices to interconnecting electronic and photonic substrates to solderless Cu to Cu assembly, predictive modeling and design, thermal management, and integration of all these into 3D Chiplet logic-memory modules, 6G Integrated 3D antenna-in package, 3D integrated power modules, and 3D energy efficient and miniaturized MEMS and sensor modules and advances in system-level electrical test.

Attendees

The conference brings global R&D, supply-chain and manufacturing, and user companies from US, Europe, Japan, Korea and Taiwan. The expected attendees include global and domestic industry executives and technical leaders as well Indian and global faculty and students. A total of about 300 attendees are expected for the 1st conference.

Hotel Radisson RED,  Sector 66,

Mohali, Punjab, India

February 29 - March 2,  2024

08:30 AM – 06:30 PM

Registration by invitation only

No Registration fees

Don’t miss it

ISPEC2024 Technical Program

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

WELCOME RECEPTION
Wednesday, 28 February 18:00 - 19:30 Hotel Radisson RED, Mohali


Inauguration by Chief Guest, Hon'ble Sh. Rajeev Chandrasekhar

  • • Minister of State for Electronics and Information Technology
  • • Minister of State for Skill Development and Entrepreneurship

Lighting Lamp     09:00 - 09:10

Charan Gurumurthy Tata
Anand Ramamoorthy Micron
Jaya Jagadish AMD
Vinay Shenoy Infineon
Ravi Bhatkal MacDermid Alpha
Vivek Sharma ST Microelectronics
Hitesh Garg NXP
Naveen Bishnoi Marvell
Veerappan V Tessolve

Tea/Coffee Break & Exhibition Inaugration 11:00 - 11:30

Can India be a Global Leader in Integrated Systems Packaging? Prof. Rao Tummala, Georgia Institute of Technology
Vision and Roadmap for SCL Sushil Pal, Joint Secretary, Ministry of Electronics & Information Technology
ISM - Indian Roadmap Akash Tripathi, CEO, India Semiconductor Mission (ISM)

Lunch Break 13:00 - 14:00

Future of Computing and AI Gokul Subramaniam, Intel
Future of Power Electronics Charan Gurumurthy, Tata Electronics
Future of Memory Devices & Package Integration w/Logic Hem Takiar, Micron
Future of 6G Communication Kapil Bhattad, Qualcomm
Overview of Global R&D Centers Prof. Abhijit Dasgupta, U. Maryland
NCREPT & GRAPES - Research, Education and Industry Collaborations Prof. Alan Mantooth, U. Arkansas
CHIMES - Research, Education and Industry Collaborations Prof. Madhavan Swaminathan, Penn State U

Tea/Coffee Break 16:30 - 17:00

S3IP - Research, Education and Industry Collaborations Prof. Bahgat Sammakia and Dr. Srikanth Rangarajan, Binghamton U
CALCE - Research, Education and Industry Collaborations Prof. Abhijit Dasgupta, U. Maryland
Georgia Tech Industry Consortium Model from Concept to Commercialization Prof. Rao Tummala, Georgia Tech
  • Panel Session: Heads of Indian Institutions
    Prof. B. S. Murty IIT Hyderabad
    Prof. Santanu Chaudhury IIT Jodhpur
    Prof. Rajeev Ahuja IIT Ropar
    Prof. Shreepad Karmalkar IIT Bhubaneswar
    Prof. V. Ramgopal Rao BITS Pilani
    Prof. Niti Nipun Sharma Manipal Academy of Higher Education

Gala Dinner 19:30 - 21:30

  • Introduction to Large Scale, Global Level Next Gen R&D in Semiconductors, Pakaging and Systems - Prof. Rao Tummala, Georgia Tech
SRA Faculty Leaders US Faculty Collaborator Industry Lead
Systems Design and Architecture Prof. Binod Kumar (IITJ)
Prof. Virendra Singh (IITB)
Prof. Anand Raghunathan (Purdue)
Prof. Vijaykrishnan Narayanan (PSU)
Sridhar Bendi (Intel)
Devices
  1. -CMOS


  2. -Power Devices

  3. -Opto-electronic

  4. -Quantum
Prof. Abhisek Dixit (IITD) & Nihar R. Mohapatra (IITGN)
Prof. Ankush Bag (IITG)
Dr. Bijoy Krishna (IITM)
Prof. Abhisek Dixit (IITD)
Prof Suman Datta (Georgia Tech)
Dr. Srinivasan Purushothaman, GlobalFoundries, USA
Electronic Substrates Prof. Pradeep Dixit (IITB)
Prof. Deepak Arora (IITJ)
Dr. Prateek Nimbalkar (Georgia Tech)
Prof. Shubhra Bansal (Purdue)
Habib Hichiri (Ajinomoto)
Nandha Mohanraj

Tea/Coffee Break 10:20 - 10:50

Thermal Management Prof Anandaroop Bhattacharya (IITKGP)
Prof. Amrit Ambirajan (IISc Bangalore)
Prof. Satish Kumar (Georgia Tech.)
Prof. Justin Weibel (Purdue University)
Dr. Shailesh Joshi (Toyota)
IC & Board Assembly and Reliability Prof. Nilesh Badwe (IITK)
Prof. Shiv Govind Singh (IITH)
Prof. Vanessa Smet (Georgia Tech)
Prof. Shubra Bansal (Purdue)
C L Gan (Micron)
6G Integrated Systems Prof. Mrinal Kanti Mandal (IITKGP)
Prof. Siddhartha P Duttagupta (IITB)
Prof. Gagan Kumar (IITG)
Prof. Madhavan Swaminathan (Penn State)
Aritra Banerjee (Univ. of Illinois Chicago)
Emmanouil M Tentzeris (Georgia Tech.)
Predictive Modeling and Design Prof. Tarun Agarwal (IITGN)
Prof. Somnath Roy (IITKGP)
Prof. Ganesh Subbarayan (Purdue)
Prof. Abhijit Dasgupta (U of Maryland)
Vamsi Krishna (Ansys)

Lunch Break 12:50 - 13:50

Integrated Sensors and MEMS Prof. Bhaskar Mitra (IITD)
Prof. Vankatesh Rao (BITS)
Power Electronics Prof. Shiladri Chakraborty (IITB)
Prof. Alan Mantooth (U. Arkansas)
Co-Packaged Optics Prof. Naresh Emani (IITH)
Prof. Sudharsanan Srinivasan (IITM)
Prof. Ajey Jacobs (USC)
Materials -Devices & Packaging Prof. Bhagwati Prasad (IISc)
Prof. Praveen Ramamurthy (IISc)
Prof. R Ramesh (Rice University)
Prof. Raj Pulugurtha (FIU)
System Level Electrical Test Prof. Jaynarayan Tudu (IITTP)
Prof. Vasu Pulijalla (NIT Nagpur)
Prof Abhijit Chatterjee (Gatech)
Prof Adit Singh (Auburn Univ)
Paresh Bharkhada - Teradyne

Tea/Coffee Break 16:20 - 16:50

  • Large Scale Global R&D Industry Consortium: Discussion about Membership Categories, Membership Costs, IP and Others

Exhibitor Reception 18:00 - 19:30

Education for Industry and Academic R&D - Industry Needs and Proposed Programmes Ravi Mahajan, Intel
Shiv Govind Singh, IITH
Skills Development for Package Manufacturing Industry Needs and Proposed Programmes Gokul Kumar, Micron
Gagan Sain, Tata Electronics
Sid Duttagupta, IITB

Infrastructure for R&D and education: Needs and proposed programmes. Ravi Bhatkal: MacDermid Alpha
Role of Industry in Academic R&D programme Nilesh Badwe, IITK

Tea/Coffee Break 10:35 - 11:05

Session Introduction: Global Packaging Supply Chain & Kickstarting the Indian Ecosystem Kuldip Johal, Session Organizers, USA
Session Introduction: Global Packaging Supply Chain & Kickstarting the Indian Ecosystem Venky Sundaram, Session Organizers, USA
Packaging Materials & Package Solution Center Model Hidenori Abe, Resonac, Japan
Polymer Materials in Advanced IC Substrates Habib Hichri, Ajinomoto, Japan
Process Chemicals and tools for advanced IC substrates Naveen Goudar, MKS/Atotech, USA/India
Solder Resists and Dielectrics for Packaging Meiten Koh, Taiyo Ink, Japan

Tea/Coffee Break 10:35 - 11:05

Materials Solutions for Semiconductor Packaging, Substrates & Assembly Ravi Bhatkal, MacDermid Alpha, USA/India
Materials for electronics assembly Ram Trichur, Henkel, USA/India
Package Solutions and Assembly Materials Takeshi Mori, Sumitomo Bakelite, Japan
Materials engineering solutions for Semiconductor/ Adv Packaging Suraj Rengarajan, Applied Materials, USA/India
Semiconductor precision processing tools Takatoshi Kyo, Disco, Singapore
Thin Film Advanced Technology Suresh Singaram, Evatec, India/Switzerland
Total solution for package Assembly Nelson Wong, K&S, Singapore
Semiconductor Assembly Equipment Chin Seng Chu, BESI, Netherlands/Singapore
Factory Automation Peter Chew, Yamaha Robotics, Japan

Lunch 13:00 - 14:00

Global Status of Memory Substrates and Plans for India Ken Lee, Simmtech, Korea
Ceramic Substrates for Semiconductor Packaging Tatsuya Okabe, Kyocera, Japan/India
Organic Substrate Manufacturing Ibrath H. A., AT&S, Austria/India
Assembly Test & Packaging Raghu Panicker, Kaynes Technologies, India
Virtualization of Chip-Package Co design for Shift Left in product development Shital Joshi, Ansys, USA/India
Integrated approach for investigating advanced package failure through correlative X-ray Microscopy and Laser Focused Ion Beam (FIB) Techniques Arun Prabha, Carl Zeiss, Germany/India
Metrology & Instruments in Semiconductor & Packaging Olivier Dulac, Ametek, France

Tea/Coffee Break 15:30 - 16:00

Dignitaries - Government

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Sh. Rajeev Chandrasekhar

CHIEF GUEST, HON’BLE SH. RAJEEV CHANDRASEKHAR

Minister of State for Electronics and Information Technology, Minister of State for Skill Development and Entrepreneurship, Government of India

Shri S. Krishnan

Secretary, Ministry of Electronics & Information Technology (MeitY)

Shri Sushil Pal

Joint Secretary, Ministry of Electronics & Information Technology (MeitY)

Akash Tripathi

CEO, India Semiconductor Mission (ISM)

PROF. ABHAY KARANDIKAR

Secretary, Department of Science and Technology (DST)

Amitesh Kumar Sinha

Executive Director, Indian Railways

Prof. Ajay Kumar Sood

Principal Scientific Advisor

S. K. Marwaha

Director, MeitY

Sunita Verma

MeitY

Surinder Singh

Advisor (Technology), India Semiconductor Mission (ISM)

Nishit Gupta

MeitY

DIGNITARIES - USERS AND MANUFACTURERS

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

GOKUL SUBRAMANIAM

Intel, India Head

CHARAN GURUMURTHY

Tata, Semiconductor Assembly & Test Head

GURSHARAN SINGH

Micron, Senior Vice President

SANDIP PATEL

IBM, India/South Asia Head

Jaya Jagadish

AMD, India Head

Vinay Shenoy

Infineon, India Head

Vivek Sharma

ST Microelectronics, India Head

JITENDRA CHADDAH

GlobalFoundries, India Head

Veerappan V

President, Tessolve

Nandha Mohanraj

Director, Western Digital

SANTOSH GUNDAPI

AT&S, India Head

RAGHU PANICKER

Kaynes SemiCon, CEO

Kapil Bhattad

Qualcomm, Director of Engineering

SANTOSH KUMAR

Texas Instruments, India Head

HITESH GARG

NXP, India Head

NAVIN BISHNOI

Marvell, India Head

Vivek Tyagi

Analog Devices

Dinanath Soni

Si2 Microsystems

Amrit Manwani

Sahasra Semiconductors Pvt. Ltd

Dignitaries - GLobal Suppliers

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Kuldip Johal

MKS/Atotech,
Session Organizer & Moderator

Venky Sundaram

Consultant,
Session Organizer & Moderator

Takatoshi Kyo

Disco, President

Hidenori Abe

Resonac, Executive Director

Nelson Wong

Nelson Wong

Kulicke & Soffa, Senior Vice President

Ken Lee

Simmtech, Executive Vice President

Habib Hichri

Ajinomoto, Vice President

Meiten Koh

Taiyo Ink.

Takeshi Mori

Executive Officer, Sumitomo Bakelite Co., Ltd.

Ram Trichur

Henkel, Head of Strategy India

Rangesh Raghavan

Lam Research, India Head

Ravi Bhatkal

MacDermid Alpha, India Head

Naveen Goudar

MKS/Atotech, India Head

Shital Joshi

Ansys, Senior Director

Tatsuya Okabe

KYOCERA Asia Pacific Pte. Ltd.

Suraj Rengarajan

Applied Material, CTO

Amit Kachroo

AARK Global Inc, CEO

Dignitaries Academia - India

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Prof. V. Kamakoti

Director, IIT Madras

Prof. B. S. Murty

Director, IIT Hyderabad

Prof. Rajat Moona

Director, IIT Gandhinagar

Prof. Santanu Chaudhury

Director, IIT Jodhpur

Prof. Rajeev Ahuja

Director, IIT Ropar

Prof. V. Ramgopal Rao

Vice Chancellor, BITS Pilani

DIGNITARIES: GLOBAL ACADEMIA AND RESEARCH CENTERS - Foreign

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Prof. Madhavan Swaminathan

Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), Penn State University

Prof. Abhijit Dasgupta

Center for Advanced Life Cycle Engineering (CALCE), University of Maryland

Prof. Suman Datta

3D Systems Packaging Research Center (PRC), Georgia Tech University

Prof. Ganesh Subbarayan

Heterogeneous Integration Electronics Packaging Centers (CHIRPS and ASIP), Purdue University

Prof. Alan Mantooth

Power Electronics Centers (NCREPT, GRAPES), University of Arkansas

Prof. Bahgat Sammakia

Small Scale Systems Integration and Packaging (S3IP), Binghamton University

Dr. Surya Bhattacharya

System-in-Package A*STAR, Institute for Microelectronics, IME

Dr. Vikas Dubey

Electronic Nano Systems (ENAS), Fraunhofer Institute

Dr. Veda S. Nagaraja

Micro-Nano Systems and PiezoMEMS, Tyndall National Institute

Sponsors & Exhibitors

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Platinum Sponsors

Gold Sponsors

Silver Sponsors

Exhibitors

R&D Leads

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Strategic Research Areas & Faculty Leaders
Session Leaders Picture
Devices
  • -CMOS
  • -Power Devices

Prof. Abhisek Dixit (IITD)
Prof. Ankush Bag (IITG)

Systems Design and Architecture Prof. B Kumar (IITJ)
Prof. Virendra Singh (IITB)
Electronic Substrates Prof. Pradeep Dixit (IITB)
Prof. Deepak Arora (IITJ)
Thermal Management Prof. Anandaroop Bhattacharya (IITKGP)
Prof. Amrit Ambirajan (IISc Bangalore)

IC and Board Assembly Prof. Nilesh Badwe (IITK)
Prof. Shiv Govind Singh (IITH)
6G Integrated Systems Prof. Mrinal Kanti Mandal (IITKGP)
Prof. Siddhartha P Duttagupta (IITB)

Predictive Modeling and Design Prof. Tarun Agarwal (IITGN)
Prof. Somnath Roy (IITKGP)
Integrated Sensors and MEMS Prof. Bhaskar Mitra (IITD)
Prof. Vankatesh Rao (BITS)
Power Electronics Prof. Shiladri Chakraborty (IITB)
Co-Packaged Optics Prof. Naresh Emani (IITH)
Prof. Sudharsanan Srinivasan (IITM)
Materials Dev & Pkg Prof. Bhagwati Prasad (IISc)
Prof. Praveen Ramamurthy (IISc)
Electrical Test Prof. Jaynarayan Tudu (IITTP)
Prof. Vasu Pulijalla (NIT Nagpur)
Education, Skill Development, Infrastructure, Industry Partnership Programs & Leaders
Session Leaders Picture
Education Prof. Shiv Govind Singh (IITH)
Skill Development Prof. Siddhartha Duttagupta (IITB)
Industry Partnership Prof. Nilesh Badwe (IITK)
Infrastructure Prof. Pradeep Dixit (IITB)
Infrastructure Dr. Ravi Bhatkal (MacDermid Alpha)
Global Academic Collaborations Prof. Shiladri Chakraborty (IITB)

Executive Committee

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Prof. Rao Tummala

Georgia Tech

Ravi Mahajan

Intel

Hem Takiar

Micron

Ravi bhatkal

MacDermid Alpha

Ashok Chandak

President, IESA

Navin Bishnoi

Marvell

Vikas Trikha

Semi-Conductor Laboratory

Organising Committee

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Prof. Rao Tummala

Georgia Tech

Prof. Abhijit Dasgupta

University of Maryland

Ravi bhatkal

MacDermid Alpha

Venky Sundaram

Anurag Awasthi

IESA

Kuldip Johal

MKS/Atotech

Gurvinder Singh

Semi-Conductor Laboratory

Dr. Manish Hooda

Semi-Conductor Laboratory

Gokul Kumar

Micron

Prof. Siddhartha Duttagupta

IITB

Prof. Nilesh Badwe

IIT Kanpur

Avinash Singh

Semi-Conductor Laboratory

Kavitha Nagarajan

IEEE EPS Chair, Intel

Sanjeev Luthra

Semi-Conductor Laboratory

Krishan Kumar

Semi-Conductor Laboratory

Arun chandrasekhar

Intel

G. P. Singh

Semi-Conductor Laboratory

Registration

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

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Nearby Places

1st India Semiconductor and Packaging Ecosystem Conference (ISPEC)

Rock garden
Rock Gardan

The Rock Garden Chandigarh is a 35 acre eco-friendly garden, built solely by home waste and other Industrial items. Sculptures are created using items such as bangles, ceramic pots, tiles, bottles and Electric waste. Garden is a mixture of Landscape, architecture, sculpture and mythology. NEK CHAND, founder of Rock Garden, started creating this garden secretly during his spare time in 1957. The Layout of Garden is based on the fantasy of a Lost Kingdom. It has 14 different chambers like the forecourt. The Teej festival, when the Rock Garden assumes a festive look, holds a special attraction for tourists.

Sukhna Lake
Sukhna Lake

Sukhna Lake is a 3 sq. km rainfed lake created in 1958 by damming the Sukhna Choe, a seasonal stream coming down from Shivalik hills. Sukhna Lake is a sanctuary for many exotic migratory birds like- Siberian Duck, Storks and Cranes during winter month. The Lake is declared National Wetland by Government of India. It’s a venue for many festive celebrations like Mango festival during monsoons. The Sukhna Lake, has longest channel for rowing and yachting events in Asia.

Capitol Complex
Capitol Complex

It’s one of the most monumental Architectural Compositions of Modern Architecture by Le Corbusier arising out of unique geo-political and cultural setting. It has been given a status of UNESCO World Heritage. The Capitol Complex is strategically located at Geographic and Topographic “Head” of the city against the back-drop of Shivalik Hills

Gandhi Bhawan
Gandhi Bhawan

The sculptural Gandhi Bhawan is placed in the heart of the Punjab University, Sector 14. Dedicated to the study of the life and works of Mahatma Gandhi this lotus shaped structure was designed by architect Pierre Jeanneret. The building represents the simplicity and purity advocated by Gandhi and showcases the entire array of Jeannerets design prowess as a bench mark of technological, formal, and aesthetic spirit of Modern architecture in Chandigarh. A must visit for lovers of architecture this building is surrounded by other outstanding examples of modern architecture like the Art Gallery, Students’ Centre and Administrative Building

For more information visit Chandigarh Tourism